View source for Motherboard 2 Digit BIOS POST codes in hex

There are devices sold that are supposed to display a bios POST code in hex format based on the stage in bootup the BIOS POST is at. For example, a BIOS POST code of 01 means that processor 1 is being tested. Most of the POST diagnostic cards have 2 digit readouts, corresponding to the list of codes below. 

Some of these motherboard POST diagnostic tools are based off of the PCI slot (also known as EISA). Other cards have the PCI slot AND a parallel port + USB port (used in conjunction), which allows for most laptops to be tested. 

Some of the cards that use these codes:

[[File:Pci-usb-parallel-post-diagnostic-card.jpg]][[File:Pci-post-diagnostic-card.jpg]]

[[Category:Software]]


==POST Diagnostic Hardware Usage==
#Power down the computer
#Plug in the POST diagnostic card
##For the PCI version, just plug into PCI slot
##For the USB/Parallel version, plug both USB and parallel in (not the PCI part)
#Power up and read the codes



==POST Diagnostic Hex Codes== 
'''The code simply shows you where the computer is in its startup process. It is the most general codes for general POST and BIOS setups. These POST hex codes will be correct for most computers'''


{|
| width="10%" valign="top" |
Code
| width="90%" valign="top" |
Meaning
|-
| width="10%" valign="top" |
01
| width="90%" valign="top" |
Processor test 1: Verify CPU status flags?aset, test, clear, and test the carry, zero, sign, overflow flags (fatal)
|-
| width="10%" valign="top" |
02
| width="90%" valign="top" |
Processor test 2: Write/read/verify all CPU registers, except SS, SP and BP with data patterns FF and 00.
|-
| width="10%" valign="top" |
03
| width="90%" valign="top" |
Calculate BIOS EPROM and sign-on message checksum; fail if not 0
|-
| width="10%" valign="top" |
04
| width="90%" valign="top" |
Test CMOS RAM interface and verify battery power Is available.
|-
| width="10%" valign="top" |
05
| width="90%" valign="top" |
Initialize chips: Disable NMI, PIE, AIE, UEI, SQWV; disable video, parity checking, and DMA: reset math coprocessor, clear all page registers and CMOS RAM shutdown byte: Initialize timers 0, 1 and 2, and set EISA timer to a known state: initialize DMA controllers 0 and 1: initialize interrupt controllers 0 and 1; initialise EISA extended registers.
|-
| width="10%" valign="top" |
06
| width="90%" valign="top" |
Test memory refresh toggle to ensure memory chips can retain data.
|-
| width="10%" valign="top" |
07
| width="90%" valign="top" |
Set up low memory; Initialize chipset early; test presence of memory; run OEM chipset initialization routines, clear lower 256K of memory; enable parity checking and test parity in lower 256K; test lower 256K memory.
|-
| width="10%" valign="top" |
08
| width="90%" valign="top" |
Setup interrupt vector table; initialize first 120 interrupt vectors with SPURlOUS_INT_HDLR and initialize INT 00-1F according to INT_TBL.
|-
| width="10%" valign="top" |
09
| width="90%" valign="top" |
Test CMOS RAM checksum and load default; if checksum is bad.
|-
| width="10%" valign="top" |
0A
| width="90%" valign="top" |
Initialize keyboard; detect type of keyboard controller (optional); set NUMLOCK status.
|-
| width="10%" valign="top" |
0B
| width="90%" valign="top" |
Initialize video interface; read CMOS RAM location 14 to find out type of video in use; detect and initialise the video adapter.
|-
| width="10%" valign="top" |
0C
| width="90%" valign="top" |
Test video memory; write signon message to screen.
|-
| width="10%" valign="top" |
0D
| width="90%" valign="top" |
OEM specific?ainitialise motherboard special chips as required by OEM; initialise cache controller early, when cache is separate from chipset.
|-
| width="10%" valign="top" |
0E
| width="90%" valign="top" |
Reserved.
|-
| width="10%" valign="top" |
0F
| width="90%" valign="top" |
Test DMA controller 0 with AA, 55, FF, 00 pattern.
|-
| width="10%" valign="top" |
10
| width="90%" valign="top" |
Test DMA controller 1 with AA, 55, FF, 00 pattern.
|-
| width="10%" valign="top" |
11
| width="90%" valign="top" |
DMA page registers?ause 1/O ports to test address circuits.
|-
| width="10%" valign="top" |
12-13
| width="90%" valign="top" |
Reserved
|-
| width="10%" valign="top" |
14
| width="90%" valign="top" |
Test 3254 timer 0 counter 2.
|-
| width="10%" valign="top" |
15
| width="90%" valign="top" |
Verify 8259 interrupt controller channel 1 by toggling interrupt Iines off/on.
|-
| width="10%" valign="top" |
16
| width="90%" valign="top" |
Verify 8259 interrupt controller channel 2 by toggling interrupt lines off/on.
|-
| width="10%" valign="top" |
17
| width="90%" valign="top" |
Test stuck 8259 interrupt bits: turn interrupt bits off and verify no interrupt mask register is on.
|-
| width="10%" valign="top" |
18
| width="90%" valign="top" |
Test 8259 functionality: force an interrupt and verify the interrupt occurred.
|-
| width="10%" valign="top" |
19
| width="90%" valign="top" |
Test stuck NMI bits (parity I/O check): verify NMI can be cleared.
|-
| width="10%" valign="top" |
1A-1E
| width="90%" valign="top" |
Reserved.
|-
| width="10%" valign="top" |
1F
| width="90%" valign="top" |
Set EISA mode: If EISA non-volatile memory checksum is good, execute EISA init. If not, execute ISA tests and clear EISA mode flat. Test EISA config mem checksum and communication ability.
|-
| width="10%" valign="top" |
20
| width="90%" valign="top" |
Initialize and enable EISA slot 0 (system board).
|-
| width="10%" valign="top" |
21-2F
| width="90%" valign="top" |
Initialize and enable EISA slots 1-15.
|-
| width="10%" valign="top" |
30
| width="90%" valign="top" |
Size base memory from 256-640K and test with various patterns.
|-
| width="10%" valign="top" |
31
| width="90%" valign="top" |
Test extended memory above 1Mb using various patterns. Press Esc to skip.
|-
| width="10%" valign="top" |
32
| width="90%" valign="top" |
If EISA mode flag set, test EISA memory found during slot initialization. Skip this by pressing Esc.
|-
| width="10%" valign="top" |
33-3B
| width="90%" valign="top" |
Reserved.
|-
| width="10%" valign="top" |
3C
| width="90%" valign="top" |
Verify CPU can switch in/out of protected, virtual 86 and 8086 page modes.
|-
| width="10%" valign="top" |
3D
| width="90%" valign="top" |
Detect if mouse is present, initialize it, and install interrupt vectors.
|-
| width="10%" valign="top" |
3E
| width="90%" valign="top" |
Initialize cache controller according to CMOS RAM setup
|-
| width="10%" valign="top" |
3F
| width="90%" valign="top" |
Enable shadow RAM according to CMOS RAM setup or if MEM TYPE is SYS in the EISA configuration information.
|-
| width="10%" valign="top" |
40
| width="90%" valign="top" |
Reserved
|-
| width="10%" valign="top" |
41
| width="90%" valign="top" |
Initialise floppy disk drive controller and any drives.
|-
| width="10%" valign="top" |
42
| width="90%" valign="top" |
Initialise hard disk drive controller and any drives.
|-
| width="10%" valign="top" |
43
| width="90%" valign="top" |
Detect and initialise serial ports.
|-
| width="10%" valign="top" |
44
| width="90%" valign="top" |
Detect and initialize parallel ports.
|-
| width="10%" valign="top" |
45
| width="90%" valign="top" |
Detect and initialise math coprocessor
|-
| width="10%" valign="top" |
46
| width="90%" valign="top" |
Print Setup message (press Ctrl-Alt-Esc to enter Setup at bottom of the screen, and enable setup.
|-
| width="10%" valign="top" |
47
| width="90%" valign="top" |
Set speed for boot.
|-
| width="10%" valign="top" |
48-4D
| width="90%" valign="top" |
Reserved.
|-
| width="10%" valign="top" |
4E
| width="90%" valign="top" |
Reboot if manufacturing POST loop pin is set. Otherwise, display any messages for non-fatal POST errors; enter setup if user pressed Ctrl-Alt-Esc.
|-
| width="10%" valign="top" |
4F
| width="90%" valign="top" |
Security check (optional): Ask for password.
|-
| width="10%" valign="top" |
50
| width="90%" valign="top" |
Write all CMOS RAM values back to CMOS RAM, and clear the screen.
|-
| width="10%" valign="top" |
51
| width="90%" valign="top" |
Preboot enable: Enable parity, NMI, cache before boot.
|-
| width="10%" valign="top" |
52
| width="90%" valign="top" |
Initialize ROMs between C80000-EFFFF. When FSCAN enabled, init from C80000 to F7FFF.
|-
| width="10%" valign="top" |
53
| width="90%" valign="top" |
Initialize time value at address 40 of BIOS RAM area.
|-
| width="10%" valign="top" |
55
| width="90%" valign="top" |
Initialize DDNIL counter to NULLs.
|-
| width="10%" valign="top" |
63
| width="90%" valign="top" |
Boot attempt: Set low stack and boot by calling INT 19.
|-
| width="10%" valign="top" |
B0
| width="90%" valign="top" |
Spurious interrupt occurred in protected mode.
|-
| width="10%" valign="top" |
B1
| width="90%" valign="top" |
Unclaimed NMI. If unmasked NMI occurs, display "Press F1 to disable NMI, F2 to boot".
|-
| width="10%" valign="top" |
BF
| width="90%" valign="top" |
Program chipset: Called by POST 7 to program chipset from CT table.
|-
| width="10%" valign="top" |
C0
| width="90%" valign="top" |
OEM specific?aTurn on/off cache.
|-
| width="10%" valign="top" |
C1
| width="90%" valign="top" |
OEM specific?aTest for memory presence and size on-board memory.
|-
| width="10%" valign="top" |
C2
| width="90%" valign="top" |
OEM specific?aInitialize board and turn on shadow and cache for fast boot.
|-
| width="10%" valign="top" |
C3
| width="90%" valign="top" |
OEM specific?aTurn on extended memory DRAM select and initialize RAM.
|-
| width="10%" valign="top" |
C4
| width="90%" valign="top" |
OEM specific?aHandle display/video switch to prevent display switch errors.
|-
| width="10%" valign="top" |
C5
| width="90%" valign="top" |
OEM specific?aFast Gate A20 handling.
|-
| width="10%" valign="top" |
C6
| width="90%" valign="top" |
OEM specific?aCache routine for setting regions that are cacheable.
|-
| width="10%" valign="top" |
C7
| width="90%" valign="top" |
OEM specific?aShadow video/system BIOS after memory proven good.
|-
| width="10%" valign="top" |
C8
| width="90%" valign="top" |
OEM specific?aHandle special speed switching.
|-
| width="10%" valign="top" |
C9
| width="90%" valign="top" |
OEM specific?aHandle normal shadow RAM operations.
|-
| width="10%" valign="top" |
D0-DF
| width="90%" valign="top" |
Debug: available POST codes for use during development.
|-
| width="10%" valign="top" |
EO
| width="90%" valign="top" |
Reserved.
|-
| width="10%" valign="top" |
E1-EF
| width="90%" valign="top" |
Setup pages: E1 = page 1, E2 = page 2, etc.
|-
| width="10%" valign="top" |
FF
| width="90%" valign="top" |
If no error flags such as memory size are set, boot via INT 19?aload system from drive A, then C; display error message if boot device not found.
|}

==External Resources==
*[http://www.etcwiki.org/images/8/89/Debug-post-codes.pdf Generic POST Codes] - Simple BIOS POST codes in hex format with descriptions
*[http://www.etcwiki.org/images/1/14/Manual_postcard_40.pdf PDF manual] - OEM specific hex POST codes for POST motherboard diagnostic cards
**Most comprehensive list of POST hex codes for all makes and models of motherboards
*[http://www.bioscentral.com/postcodes/amibios.htm AMIbios post codes] - List of hex POST codes for diagnostic cards
*[http://www.bioscentral.com/postcodes/dellbios.htm Dell POST codes] - Hex and beep codes for Dell motherboards
*[http://www.bioscentral.com/postcodes/awardbios.htm AwardBIOS POST codes] - Hex and beep codes for POST on AwardBIOS based bios
*[http://www.bioscentral.com/postcodes/hpbios.htm HP BIOS POST codes] - Hex POST codes and beep codes for HP motherboards
*[http://www.bioscentral.com/postcodes/phoenixbios.htm Phoenix BIOS POST codes] - Hex POST codes for Phoenix Bios motherboard diagnostics
*[http://www.bioscentral.com/postcodes/ibmbios.htm IBM BIOS POST codes] - For IBM computers using IBM bios, hex POST codes